In advanced technologies, electronic fuses (e-fuses) have been implemented at the polysilicon (PC) level. During programming, a high current pulse of short duration is passed through the structure, which irreversibly migrates silicide on top of the PC level. This migration, in turn, causes a change in resistance and thus acts as a programmable fuse. However, as scaling progresses, it becomes harder to implement these e-fuses at the silicon level due to a drop in maximum allowable currents through a lower metal layer, M1. Also, the collateral damage associated with the blowing of the fuse is becoming more difficult to contain.
In a conventional metal fuse approach as shown, for example, in FIG. 19, a two-level structure is used in which the electron flow is from the interconnect structure (via) into the wire line. A high current would be applied between the I+ and I− connections to induce electromigration (EM) failure and the voltage across the structure would be measured using the V+ and V− connections. In such a structure, most of the failures should occur in the interconnect structure (via); however, some of these failures also occur in the wire line. The failures in the wire line, though, are less desirable since the cap layer, such as silicon nitride (Si3N4) or silicon carbide (SiC) may be compromised during the programming process. This lack of control over the failure location will lead to variability in the final resistance of the fuse structure after programming. Also, even if all failures occur in the interconnect structure (via), there can still be a large variability in the resistance of the fuse after the blow process, which may suggest that some of the vias did not fail completely.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.